The RSP is a part of the N64's Reality Co-Processor (RCP), which is a slave processor to the main R4300i CPU.

• Runs at 2/3 the speed of the R4300i, specifically at 62.5 MHz.
• Does not have a floating-point unit, but instead has a vector unit to do operations in parallel.
• Runs instructions off of IMEM(4Kb), so the PC counter is only 12 bits wide. Any higher bits in a address get ignored.
• Cannot directly read memory from RDRAM, the programmer must initiate a DMA to transfer memory between RDRAM and DMEM(4Kb).
• The general purpose registers are 32-bit wide, not 64-bit.
• Has no support for interrupts, traps, or exceptions.
• Modified Instructions:
  • ADD/ADDU, ADDI/ADDIU, SLTI/SLTIU, SUB/SUBU are the same, since the RSP does not generate an overflow exception.
  • BREAK does not generate a trap, instead it is used to set bits in the RSP status register and signals an interrupt to the CPU.
• Missing Instructions:
  • All 64-bit instructions
    • LD, SD, LDC1, LDC2, SDC1, SDC2, DADDI, DADDIU, DSLLV, DSRLV, DSRAV, DMULT, DMULTU, DDIV, DDIVU, DADD, DADDU, DSUB, DSUBU, DSLL, DSRL, DSRA, DSLL32, DSRL32, DSRA32
  • load/store left & right, and load locked
    • LDL, LDR, LWL, LWR, LWU, SWL, SDL, SDR, SWR, LL, LLD
  • Store conditionals
    • SC, SCD
  • Likely branches
    • BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, BGTZALL, BGEZALL
  • HI and LO register moves
    • MFHI, MTHI, MFLO, MTLO
  • Multiply/Divide
    • MULT, MULTU, DIV, DIVU
  • SYSCALL, since the RSP does not generate exceptions
  • SYNC
  • Branch on co-processor
    • BCzF, BCzT
  • Trap
    • TGE, TGEU, TLT, TLTU, TEQ, TNE, TGEI, TGEIU, TLTI, TLTIU, TEQI, TNEI

The RSP contains two 4 Kilobyte caches referred to IMEM (Instruction Memory) and DMEM (Data memory).

Like the names suggest, IMEM can only be used for RSP instructions and DMEM can only be used for data. These caches can only be accessed by the RSP, and cannot be accessed externally.

There are 32 general purpose vector registers, each of them 128-bits wide.

A VU register can be accessed in different ways depending on the instruction.

For most computational instructions, like add or multiply, vector elements are used. This allows the RSP to perform 8 computational operations in one instruction. For example,

// Lets say that $v0 contains [0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007] 
//           and $v1 contains [0x0100, 0x0100, 0x0100, 0x0100, 0x0100, 0x0100, 0x0100, 0x0100]

vadd $v2, $v0, $v1 // Vector add instruction

// $v2 now contains [0x0100, 0x0101, 0x0102, 0x0103, 0x0104, 0x0105, 0x0106, 0x0107]

You can also do operations with a subsets of a register with scalar halves (h) and scalar quarters (q).

For example,

// Computing 2 distances between 2 pairs of 3D points:
// Distance = sqrt((xa-xb)² + (ya-yb)² + (za-zb)²)
// $v0 = [ xa1, ya1, za1, 0, xa2, ya2, za2, 0 ]
// $v1 = [ xb1, yb1, zb1, 0, xb2, yb2, zb2, 0 ]

vsub $v2, $v0, $v1 // Subtract $v1 from $v0

// $v2 = [ xa1-xb1, ya1-yb1, za1-zb1, 0, xa2-xb2, ya2-yb2, za2-zb2, 0 ]

vmudh $v2, $v2, $v2 // Multiply $v2 by itself

// $v2 = [ (xa1-xb1)², (ya1-yb1)², (za1-zb1)², 0, (xa2-xb2)², (ya2-yb2)², (za2-zb2)², 0 ]

// To make things simpler: xN' = (xaN-xbN)², yN' = (yaN-ybN)², and zN' = (zaN-zbN)²

// Now we add the y terms to the x terms using $v2[1q]
// $v2[1q] = [y1', y1', 0, 0, y2', y2', 0, 0]

vadd $v2, $v2, $v2[1q]

// $v2 = [ x1' + y1', 2(y1'), z1', 0, x2' + y2', 2(y2'), z2', 0 ]

// Then we add the z terms to the x+y terms using $v2[2h]
// $v2[2h] = [z1', z1', z1', z1', z2', z2', z2', z2']

vadd $v2, $v2, $v2[2h]

// $v2 = [ x1' + y1' + z1', 2(y1') + z1', 2(z1'), z1', x2' + y2' + z2', 2(y2') + z2', 2(z2'), z2' ]

// To get the square root of X, you have to compute 1/SQRT(X) and multiply it by X.
// Note: we only care about elements 0 and 4 at this point.

vrsq $v3, $v2[0h] // Calculate 1/SQRT

// rsq1 = 1/sqrt(x1' + y1' + z1'), rsq2 = 1/sqrt(x2' + y2' + z2')
// $v3 = [ rsq1, rsq1, rsq1, rsq1, rsq2, rsq2, rsq2, rsq2 ]

vmudh $v3, $v3, $v2[0h] // Multiply to get final answer

// sqrt1 = sqrt(x1' + y1' + z1'), sqrt2 = sqrt(x2' + y2' + z2')
// $v3 = [sqrt1, sqrt1, sqrt1, sqrt1, sqrt2, sqrt2, sqrt2, sqrt2]

// The distance for the first set of points is in $v3[0] and the distance for the second set is in $v3[4].

// Do note that these 6 instructions will take 24 cycles due to data hazards stalling the pipeline.
// Inserting a few unrelated instructions in-between these instructions will get you better performance.

For Vector Load/Store Commands, [e] refers to the byte index of the vector register not the element index.

In the pseudo code in the some of some of following commands, the variable j depends on the scalar element.
(Note that e is a 4-bit number)

if (e == 0):
  j = i;
elseif ((e3 & 0b1110) == 0b0010): // Scalar Quarter
  j = (e & 0b0001) + (i & 0b1110);
elseif ((e3 & 0b1100) == 0b0100): // Scalar Half
  j = (e & 0b0011) + (i & 0b1100);
elseif ((e3 & 0b1000) == 0b1000): // Scalar Whole
  j = e & 0b0111;
endif

For Vector Computational Commands, [e] refers to the element index.

Avoiding pipeline stalls in software can be accomplished by understanding the following rules.

1.) VU register destination writes 4 cycles later (need 3 cycles between load and use). 
    This applies to vector computational instructions, vector loads, and coprocessor 2 moves (mtc2).
    
      For example,
    
      llv $v0[0], 0x00($r0) | llv $v0[0], 0x00($r0)
      /* Stall here */      | llv $v2[0], 0x04($r0)
      /* Stall here */      | llv $v3[0], 0x08($r0)
      /* Stall here */      | llv $v4[0], 0x0C($r0)
      addv $v1, $v0, $v0    | addv $v1, $v0, $v0
    
      Both of these sections of code take up the same number of cycles in the RSP. It is better to have 
      unrelated instructions in-between the vector opcodes to improve efficiency, even though it might
      reduce code readability. 
    
2.) SU register load takes 3 cycles (need 2 cycles between load and use). This applies to SU loads 
    and coprocessor moves (mfc0, cfc2, mfc2). SU computational results are available in the next cycle.
    
      lw $t0, 0x00($r0) | lw $t0, 0x00($r0)
      /* Stall here */  | lw $t4, 0x04($r0)
      /* Stall here */  | add $t6, $t2, $t1
      addi $t1, $t0, 1  | addi $t1, $t0, 1
    
      Like rule #1, inserting unrelated instructions between a load and a use is more efficient. 
      However, the following is ok due to pipeline forwarding:
    
      addi $t1, $t0, 1
      sw $t1, 0x00($r0)
    
    
3.) Any load followed by any store 2 cycles later, causes a one cycle bubble. Coprocessor moves 
    (mtc0, mfc0, mtc2, mfc2, ctc2, cfc2) count as both loads and stores.
    
      lw $t0, 0x40(r0)
      addi $t1, $t1, 0x01
      /* Stall here due to the lw above */
      sw $t1, 0x30(r0)
    
4.) A branch target not 64-bit aligned always single issues.

5.) Branches:
  - Can dual issue (with preceding instruction).
  - No branch instruction permitted in a delay slot.
  - Delay slot always single issues.
  - Taken branch causes a 1 cycle bubble.