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r4300

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MIPS R4300i CPU

Command Definition Pseudo code
ADD rd, rs, rt Add rd = rs + rt
ADDU rd, rs, rt Add Unsigned rd = rs + rt
ADDI rt, rs, immediate Add Immediate rd = rs + immediate
ADDIU rt, rs, immediate Add Immediate Unsigned rd = rs + immediate
SUB rd, rs, rt Subtract rd = rs - rt
SUBU rd, rs, rt Subtract Unsigned rd = rs - rt
MULT rs, rt Multiply lo = rs * rt
MULTU rs, rt Multiply Unsigned lo = rs * rt
DIV rs, rt Divide lo = rs / rt; hi = rs % rt
DIVU rs, rt Divide Unsigned lo = rs / rt; hi = rs % rt
AND rd, rs, rt And rd = rs & rt
ANDI rt, rs, immediate And Immediate rt = rs & immediate
OR rd, rs, rt Or rd = rs | rt
ORI rt, rs, immediate Or Immediate rt = rs | immediate
XOR rd, rs, rt Exclusive Or rd = rs ^ rt
XORI rt, rs, immediate Exclusive Or Immediate rd = rs ^ immediate
NOR rd, rs, rt Nor rd = ~(rs | rt)
SLL rd, rt, sa Shift Left Logical rd = rt << sa
SLLV rd, rt, rs Shift Left Logical Variable rd = rt << rs
SRA rd, rt, sa Shift Right Arithmetic rd = (int32)rt >> sa
SRAV rd, rt, rs Shift Right Arithmetic Variable rd = (int32)rt >> rs
SRL rd, rt, sa Shift Right Logical rd = (uint32)rt >> sa
SRLV rd, rt, rs Shift Right Logical Variable rd = (uint32)rt >> rs
SLT rd, rs, rt Set On Less Than rd = (rs < rt) ? 1 : 0
SLTU rd, rs, rt Set On Less Than Unsigned rd = (rs < rt) ? 1 : 0
SLTI rt, rs, immediate Set On Less Than Immediate rd = (rs < immediate) ? 1 : 0
SLTIU rt, rs, immediate Set On Less Than Immediate Unsigned rd = (rs < immediate) ? 1 : 0
DADD rd, rs, rt Doubleword Add
DADDU rd, rs, rt Doubleword Add Unsigned
DADDI rt, rs, immediate Doubleword Add Immediate
DADDIU rt, rs, immediate Doubleword Add Immediate Unsigned
DSUB rd, rs, rt Doubleword Subtract
DSUBU rd, rs, rt Doubleword Subtract Unsigned
DMULT rs, rt Doubleword Multiply
DMULTU rs, rt Doubleword Multiply Unsigned
DDIV rs, rt Doubleword Divide
DDIVU rs, rt Doubleword Divide Unsigned
DSLL rd, rt, sa Doubleword Shift Left Logical
DSLL32 rd, rt, sa Doubleword Shift Left Logical + 32
DSLLV rd, rt, rs Doubleword Shift Left Logical Variable
DSRA rd, rt, sa Doubleword Shift Right Arithmetic
DSRA32 rd, rt, sa Doubleword Shift Right Arithmetic + 32
DSRAV rd, rt, rs Doubleword Shift Right Arithmetic Variable
DSRL rd, rt, sa Doubleword Shift Right Logical
DSRL32 rd, rt, sa Doubleword Shift Right Logical + 32
DSRLV rd, rt, rs Doubleword Shift Right Logical Variable
MFHI rd Move From HI rd = hi
MFLO rd Move From LO rd = lo
MTHI rs Move To HI hi = rs
MTLO rs Move To LO lo = rs
LUI rt, immediate Load Upper Immediate rt = immediate << 16
LB rt, offset(base) Load Byte rt = *(int8*)(base + offset)
LBU rt, offset(base) Load Byte Unsigned rt = *(uint8*)(base + offset)
LH rt, offset(base) Load Halfword rt = *(int16*)(base + offset)
LHU rt, offset(base) Load Halfword Unsigned rt = *(uint16*)(base + offset)
LW rt, offset(base) Load Word rt = *(int32*)(base + offset)
LWU rt, offset(base) Load Word Unsigned rt = *(uint32*)(base + offset)
LWC1 ft, offset(base) Load Word To FPU (Coprocessor 1) ft = *(float*)(base + offset)
LWL rt, offset(base) Load Word Left
LWR rt, offset(base) Load Word Right
LD rt, offset(base) Load Doubleword rt = *(uint64*)(base + offset)
LDC1 ft, offset(base) Load Doubleword To FPU (Coprocessor 1) ft = *(double*)(base + offset)
LDL rt, offset(base) Load Doubleword Left
LDR rt, offset(base) Load Doubleword Right
LL rt, offset(base) Load Linked
LLD rt, offset(base) Load Linked Doubleword
SB rt, offset(base) Store Byte *(int8*)(base + offset) = rt
SH rt, offset(base) Store Halfword *(int16*)(base + offset) = rt
SW rt, offset(base) Store Word *(int32*)(base + offset) = rt
SWC1 ft, offset(base) Store Word From FPU (Coprocessor 1) *(float*)(base + offset) = ft
SWL rt, offset(base) Store Word Left
SWR rt, offset(base) Store Word Right
SD rt, offset(base) Store Doubleword *(int64*)(base + offset) = rt
SDC1 ft, offset(base) Store Doubleword From FPU (Coprocessor 1)
SDL rt, offset(base) Store Doubleword Left
SDR rt, offset(base) Store Doubleword Right
SC rt, offset(base) Store Conditional
SCD rt, offset(base) Store Conditional Doubleword
J target Jump RA = target
JR rs Jump Register PC = rs
JAL target Jump And Link RA = PC + 8; PC = target
JALR rs Jump And Link Register rd = PC + 8; PC = rs
JALR rd, rs Jump And Link Register rd = PC + 8; PC = rs
BEQ rs, rt, offset Branch On Equal if(rs == rt) PC = offset
BEQL rs, rt, offset Branch On Equal Likely if(rs == rt) PC = offset
BGTZ rs, offset Branch On Greater Than Zero if(rs > 0) PC = offset
BGTZL rs, offset Branch On Greater Than Zero Likely if(rs > 0) PC = offset
BLEZ rs, offset Branch On Less Than Or Equal To Zero if(rs <= 0) PC = offset
BLEZL rs, offset Branch On Less Than Or Equal To Zero Likely if(rs <= 0) PC = offset
BGEZ rs, offset Branch On Greater Than Or Equal To Zero if(rs >= 0) PC = offset
BGEZL rs, offset Branch On Greater Than Or Equal To Zero Likely if(rs >= 0) PC = offset
BGEZAL rs, offset Branch On Greater Than Or Equal To Zero And Link if(rs >= 0) {
RA = PC + 8; PC = offset
}
BGEZALL rs, offset Branch On Greater Than Or Equal To Zero And Link Likely if(rs >= 0) {
RA = PC + 8; PC = offset
}
BLTZ rs, offset Branch On Less Than Zero if(rs < 0) PC = offset
BLTZL rs, offset Branch On Less Than Zero Likely if(rs < 0) PC = offset
BLTZAL rs, offset Branch On Less Than Zero And Link if(rs < 0) {
RA = PC + 8; PC = offset
}
BLTZALL rs, offset Branch On Less Than Zero And Link Likely if(rs < 0) {
RA = PC + 8; PC = offset
}
BNE rs, rt, offset Branch On Not Equal
BNEL rs, rt, offset Branch On Not Equal Likely
MFC1 rt, fs Move Word From FPU (Coprocessor 1)
DMFC1 rt, fs Doubleword Move From FPU (Coprocessor 1)
MTC1 rt, fs Move To FPU (Coprocessor 1)
DMTC1 rt, fs Doubleword Move To FPU (Coprocessor 1)
CFC1 rt, fs Move Control Word From FPU (Coprocessor 1)
CTC1 rt, fs Move Control Word To FPU (Coprocessor 1)
MOV.fmt fd, fs Floating-point Move
ABS.fmt fd, fs Floating-point Absolute Value
NEG.fmt fd, fs Floating-point Negate
SQRT.fmt fd, fs Floating-point Square Root
ADD.fmt fd, fs, ft Floating-point Add
SUB.fmt fd, fs, ft Floating-point Subtract
MUL.fmt fd, fs, ft Floating-point Multiply
DIV.fmt fd, fs, ft Floating-point Divide
CVT.S.fmt fd, fs Floating-point Convert To Single Floating-point Format
CVT.D.fmt fd, fs Floating-point Convert To Double Floating-point Format
CVT.W.fmt fd, fs Floating-point Convert To Single Fixed-point Format
CVT.L.fmt fd, fs Floating-point Convert To Long Fixed-point Format
FLOOR.L.fmt fd, fs Floating-point Floor To Long Fixed-point Format
FLOOR.W.fmt fd, fs Floating-point Floor To Single Fixed-point Format
ROUND.L.fmt fd, fs Floating-point Round To Long Fixed-point Format
ROUND.W.fmt fd, fs Floating-point Round To Single Fixed-point Format
TRUNC.L.fmt fd, fs Floating-point Truncate To Long Fixed-point Format
TRUNC.W.fmt fd, fs Floating-point Truncate To Single Fixed-point Format
CEIL.L.fmt fd, fs Floating-point Ceiling To Long Fixed-point Format
CEIL.W.fmt fd, fs Floating-point Ceiling To Single Fixed-point Format
C.F.fmt fs, ft Floating-point Compare False
C.UN.fmt fs, ft Floating-point Compare Unordered
C.EQ.fmt fs, ft Floating-point Compare Equal
C.UEQ.fmt fs, ft Floating-point Compare Unordered or Equal
C.OLT.fmt fs, ft Floating-point Compare Ordered Less Than
C.ULT.fmt fs, ft Floating-point Compare Unordered Less Than
C.OLE.fmt fs, ft Floating-point Compare Unordered or Less Than
C.ULE.fmt fs, ft Floating-point Compare Unordered or Less Than or Equal
C.SF.fmt fs, ft Floating-point Compare Signaling False
C.NGLE.fmt fs, ft Floating-point Compare Not Greater Than or Less Than or Equal
C.SEQ.fmt fs, ft Floating-point Compare Signaling Equal
C.NGL.fmt fs, ft Floating-point Compare Not Greater Than or Less Than
C.LT.fmt fs, ft Floating-point Compare Less Than
C.NGE.fmt fs, ft Floating-point Compare Not Greater Than or Equal
C.LE.fmt fs, ft Floating-point Compare Less Than or Equal
C.NGT.fmt fs, ft Floating-point Compare Not Greater Than
BC1F offset Branch On FPU False (Coprocessor 1)
BC1FL offset Branch On FPU False Likely (Coprocessor 1)
BC1T offset Branch On FPU True (Coprocessor 1)
BC1TL offset Branch On FPU True Likely (Coprocessor 1)
MFC0 rt, rd Move From Coprocessor 0
MTC0 rt, rd Move To Coprocessor 0
CACHE op, offset(base) Cache Operation
TEQ rs, rt Trap If Equal
TEQI rs, immediate Trap If Equal Immediate
TGE rs, rt Trap If Greater Than Or Equal
TGEI rs, immediate Trap If Greater Than Or Equal
TGEIU rs, immediate Trap If Greater Than Or Equal
TGEU rs, rt Trap If Greater Than Or Equal Unsigned
TLT rs, rt Trap If Less Than
TLTI rs, immediate Trap If Less Than Immediate
TLTIU rs, immediate Trap If Less Than Immediate Unsigned
TLTU rs, rt Trap If Less Than Unsigned
TNE rs, rt Trap If Not Equal
TNEI rs, immediate Trap If Not Equal Immediate
SYNC Synchronize (No operation on R4300)
SYSCALL System Call COP0_CAUSE |= (8 << 2);
COP0_EPC = PC;
PC = exc_vector_base + 0x180
BREAK Breakpoint COP0_CAUSE |= (9 << 2);
COP0_EPC = PC;
PC = exc_vector_base + 0x180
ERET Return From Exception PC = COP0_EPC (or COP0_ERROREPC)
TLBP Probe TLB For Matching Entry
TLBR Read Indexed TLB Entry
TLBWI Write Indexed TLB Entry
TLBWR Write Random TLB Entry
r4300.1549532444.txt.gz · Last modified: 2019/02/07 09:40 by shygoo

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