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r4300 [2019/02/09 20:28] shygoo add pseudo code for most commands, FPR, FCR31 |
r4300 [2019/05/06 17:54] shygoo [Interrupts] clarify MI_INTR_MASK_REG usage |
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==== Interrupts ==== | ==== Interrupts ==== | ||
^Cause bit^Source ^ | ^Cause bit^Source ^ | ||
- | |IP7 |Timer interrupt| | ||
- | |IP6 |Int4 pin <color lightgreen>(N64: RDB Write)</color>| | ||
- | |IP5 |Int3 pin <color lightgreen>(N64: RDB Read)</color>| | ||
- | |IP4 |Int2 pin <color lightgreen>(N64: Pre-NMI (Reset button))</color>| | ||
- | |IP3 |Int1 pin <color lightgreen>(N64: Cartridge)</color>| | ||
- | |IP2 |Int0 pin <color lightgreen>(N64: RCP)</color>| | ||
- | |IP1 |Set by software| | ||
|IP0 |Set by software| | |IP0 |Set by software| | ||
+ | |IP1 |Set by software| | ||
+ | |IP2 |Int0 pin <color lightgreen>(N64: RCP)</color>| | ||
+ | |IP3 |Int1 pin <color lightgreen>(N64: Cartridge)</color>| | ||
+ | |IP4 |Int2 pin <color lightgreen>(N64: Pre-NMI (Reset button))</color>| | ||
+ | |IP5 |Int3 pin <color lightgreen>(N64: RDB Read)</color>| | ||
+ | |IP6 |Int4 pin <color lightgreen>(N64: RDB Write)</color>| | ||
+ | |IP7 |Timer interrupt| | ||
+ | |||
+ | * Software interrupts (IP1:IP0) are generated when software manually sets the Cause register's IP1 or IP0 bit to 1 using an MTC0 instruction. | ||
+ | * The Timer interrupt (IP7) is generated when the Count and Compare registers are equal. | ||
+ | * Interrupts may be masked by setting the respective IM bits of the Status register to 0. | ||
- | Any of these may be masked by setting the corresponding IM bit of the Status register to 0. | ||
- | The Timer interrupt is generated when the Count and Compare register are equal. | ||
<color lightgreen> | <color lightgreen> | ||
- | On the Nintendo 64, IP2 represents an RCP (Reality Coprocessor) interrupt. When an RCP interrupt occurs, a flag representing the specific RCP interface is written to MI_INTR_REG (0x04300008). | + | On the Nintendo 64, IP2 represents an RCP (Reality Coprocessor) interrupt. When an RCP interrupt occurs, a flag representing the specific RCP interface may be read from MI_INTR_REG (0x04300008). |
</color> | </color> | ||
^<color lightgreen>Bit</color>^<color lightgreen>Name</color>^<color lightgreen>Description</color>^ | ^<color lightgreen>Bit</color>^<color lightgreen>Name</color>^<color lightgreen>Description</color>^ | ||
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|<color lightgreen>0x10</color>|<color lightgreen>MI_INTR_PI</color>|<color lightgreen>Peripheral Interface - ROM to RAM DMA done</color>| | |<color lightgreen>0x10</color>|<color lightgreen>MI_INTR_PI</color>|<color lightgreen>Peripheral Interface - ROM to RAM DMA done</color>| | ||
|<color lightgreen>0x20</color>|<color lightgreen>MI_INTR_DP</color>|<color lightgreen>Display Processor - RDP processing done (gDPFullSync)</color>| | |<color lightgreen>0x20</color>|<color lightgreen>MI_INTR_DP</color>|<color lightgreen>Display Processor - RDP processing done (gDPFullSync)</color>| | ||
+ | |||
<color lightgreen> | <color lightgreen> | ||
- | RCP-specific interrupts may be masked by setting the corresponding bits in MI_INTR_MASK_REG (0x0430000C) to 0. | + | RCP-specific interrupts may be enabled or disabled by writing one or more of the following values to MI_INTR_MASK_REG (0x0430000C). |
</color> | </color> | ||
+ | ^<color lightgreen>Bit</color>^<color lightgreen>Name</color>^<color lightgreen>Description</color>^ | ||
+ | |<color lightgreen>0x0001</color>|<color lightgreen>MI_INTR_MASK_CLR_SP</color>|<color lightgreen>Disable SP interrupts</color>| | ||
+ | |<color lightgreen>0x0002</color>|<color lightgreen>MI_INTR_MASK_SET_SP</color>|<color lightgreen>Enable SP interrupts</color>| | ||
+ | |<color lightgreen>0x0004</color>|<color lightgreen>MI_INTR_MASK_CLR_SI</color>|<color lightgreen>Disable SI interrupts</color>| | ||
+ | |<color lightgreen>0x0008</color>|<color lightgreen>MI_INTR_MASK_SET_SI</color>|<color lightgreen>Enable SI interrupts</color>| | ||
+ | |<color lightgreen>0x0010</color>|<color lightgreen>MI_INTR_MASK_CLR_AI</color>|<color lightgreen>Disable AI interrupts</color>| | ||
+ | |<color lightgreen>0x0020</color>|<color lightgreen>MI_INTR_MASK_SET_AI</color>|<color lightgreen>Enable AI interrupts</color>| | ||
+ | |<color lightgreen>0x0040</color>|<color lightgreen>MI_INTR_MASK_CLR_VI</color>|<color lightgreen>Disable VI interrupts</color>| | ||
+ | |<color lightgreen>0x0080</color>|<color lightgreen>MI_INTR_MASK_SET_VI</color>|<color lightgreen>Enable VI interrupts</color>| | ||
+ | |<color lightgreen>0x0100</color>|<color lightgreen>MI_INTR_MASK_CLR_PI</color>|<color lightgreen>Disable PI interrupts</color>| | ||
+ | |<color lightgreen>0x0200</color>|<color lightgreen>MI_INTR_MASK_SET_PI</color>|<color lightgreen>Enable PI interrupts</color>| | ||
+ | |<color lightgreen>0x0400</color>|<color lightgreen>MI_INTR_MASK_CLR_DP</color>|<color lightgreen>Disable DP interrupts</color>| | ||
+ | |<color lightgreen>0x0800</color>|<color lightgreen>MI_INTR_MASK_SET_DP</color>|<color lightgreen>Enable DP interrupts</color>| | ||
---- | ---- | ||
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* https://level42.ca/projects/ultra64/Documentation/man/pro-man/pro07/index7.8.html | * https://level42.ca/projects/ultra64/Documentation/man/pro-man/pro07/index7.8.html | ||
* https://level42.ca/projects/ultra64/Documentation/man/n64man/u64/u64.html | * https://level42.ca/projects/ultra64/Documentation/man/n64man/u64/u64.html | ||
+ | * https://level42.ca/projects/ultra64/Documentation/man/header/rcp.htm | ||
* https://github.com/n64dev/cen64/blob/72c778c3bfb25262498af6a21e8dec828a28be19/vr4300/interface.h#L16 | * https://github.com/n64dev/cen64/blob/72c778c3bfb25262498af6a21e8dec828a28be19/vr4300/interface.h#L16 | ||
* http://ti.ira.uka.de/TI-2/Mips/Befehlssatz.pdf | * http://ti.ira.uka.de/TI-2/Mips/Befehlssatz.pdf | ||