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r4300 [2019/02/09 20:28] shygoo add pseudo code for most commands, FPR, FCR31 |
r4300 [2019/02/12 18:11] shygoo better information on rcp interrupt masking |
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| |IP0 |Set by software| | |IP0 |Set by software| | ||
| - | Any of these may be masked by setting the corresponding IM bit of the Status register to 0. | + | * The Timer interrupt (IP7) is generated when the Count and Compare registers are equal. |
| - | The Timer interrupt is generated when the Count and Compare register are equal. | + | * Software interrupts (IP1:IP0) are generated when software manually sets the Cause register's IP1 or IP0 bit to 1 using an MTC0 instruction. |
| + | * Interrupts may be masked by setting the corresponding IM bits of the Status register to 0. | ||
| <color lightgreen> | <color lightgreen> | ||
| Line 399: | Line 401: | ||
| |<color lightgreen>0x10</color>|<color lightgreen>MI_INTR_PI</color>|<color lightgreen>Peripheral Interface - ROM to RAM DMA done</color>| | |<color lightgreen>0x10</color>|<color lightgreen>MI_INTR_PI</color>|<color lightgreen>Peripheral Interface - ROM to RAM DMA done</color>| | ||
| |<color lightgreen>0x20</color>|<color lightgreen>MI_INTR_DP</color>|<color lightgreen>Display Processor - RDP processing done (gDPFullSync)</color>| | |<color lightgreen>0x20</color>|<color lightgreen>MI_INTR_DP</color>|<color lightgreen>Display Processor - RDP processing done (gDPFullSync)</color>| | ||
| + | |||
| <color lightgreen> | <color lightgreen> | ||
| - | RCP-specific interrupts may be masked by setting the corresponding bits in MI_INTR_MASK_REG (0x0430000C) to 0. | + | RCP-specific interrupts may be masked or unmasked by writing one or more of the following values to MI_INTR_MASK_REG (0x0430000C). |
| </color> | </color> | ||
| + | ^<color lightgreen>Bit</color>^<color lightgreen>Name</color>^<color lightgreen>Description</color>^ | ||
| + | |<color lightgreen>0x0001</color>|<color lightgreen>MI_INTR_MASK_CLR_SP</color>|<color lightgreen>Clear SP mask</color>| | ||
| + | |<color lightgreen>0x0002</color>|<color lightgreen>MI_INTR_MASK_SET_SP</color>|<color lightgreen>Set SP mask</color>| | ||
| + | |<color lightgreen>0x0004</color>|<color lightgreen>MI_INTR_MASK_CLR_SI</color>|<color lightgreen>Clear SI mask</color>| | ||
| + | |<color lightgreen>0x0008</color>|<color lightgreen>MI_INTR_MASK_SET_SI</color>|<color lightgreen>Set SI mask</color>| | ||
| + | |<color lightgreen>0x0010</color>|<color lightgreen>MI_INTR_MASK_CLR_AI</color>|<color lightgreen>Clear AI mask</color>| | ||
| + | |<color lightgreen>0x0020</color>|<color lightgreen>MI_INTR_MASK_SET_AI</color>|<color lightgreen>Set AI mask</color>| | ||
| + | |<color lightgreen>0x0040</color>|<color lightgreen>MI_INTR_MASK_CLR_VI</color>|<color lightgreen>Clear VI mask</color>| | ||
| + | |<color lightgreen>0x0080</color>|<color lightgreen>MI_INTR_MASK_SET_VI</color>|<color lightgreen>Set VI mask</color>| | ||
| + | |<color lightgreen>0x0100</color>|<color lightgreen>MI_INTR_MASK_CLR_PI</color>|<color lightgreen>Clear PI mask</color>| | ||
| + | |<color lightgreen>0x0200</color>|<color lightgreen>MI_INTR_MASK_SET_PI</color>|<color lightgreen>Set PI mask</color>| | ||
| + | |<color lightgreen>0x0400</color>|<color lightgreen>MI_INTR_MASK_CLR_DP</color>|<color lightgreen>Clear DP mask</color>| | ||
| + | |<color lightgreen>0x0800</color>|<color lightgreen>MI_INTR_MASK_SET_DP</color>|<color lightgreen>Set DP mask</color>| | ||
| ---- | ---- | ||
| Line 421: | Line 437: | ||
| * https://level42.ca/projects/ultra64/Documentation/man/pro-man/pro07/index7.8.html | * https://level42.ca/projects/ultra64/Documentation/man/pro-man/pro07/index7.8.html | ||
| * https://level42.ca/projects/ultra64/Documentation/man/n64man/u64/u64.html | * https://level42.ca/projects/ultra64/Documentation/man/n64man/u64/u64.html | ||
| + | * https://level42.ca/projects/ultra64/Documentation/man/header/rcp.htm | ||
| * https://github.com/n64dev/cen64/blob/72c778c3bfb25262498af6a21e8dec828a28be19/vr4300/interface.h#L16 | * https://github.com/n64dev/cen64/blob/72c778c3bfb25262498af6a21e8dec828a28be19/vr4300/interface.h#L16 | ||
| * http://ti.ira.uka.de/TI-2/Mips/Befehlssatz.pdf | * http://ti.ira.uka.de/TI-2/Mips/Befehlssatz.pdf | ||
r4300.txt · Last modified: 2019/05/06 17:54 by shygoo